There is a general need for materials with low dielectric constants (low-k values) for use in the integrated circuits (ICs). Using low-k materials as the interlayer dielectric reduces the delay in signal propagation and signal crosstalk due to capacitive effects. The lower the dielectric constant of the dielectric layer, the lower the capacitance and the lower the RC delay in the lines and signal crosstalk between electrical lines of the IC. Further, the use of low-k materials as interlayer dielectric will reduce power consumption of complex integrated circuits.
Low-k dielectrics are conventionally defined as those materials that have a dielectric constant (k) lower than that of silicon dioxide (SiO2), that is k<˜4. For most current applications in the IC industry, they should have a dielectric constant of 3 or less. Typical methods of obtaining low-k materials include introducing pores into the dielectric matrix and/or doping silicon dioxide with various hydrocarbons or fluorine. In technology nodes of 90 nanometers and beyond, carbon doped oxide dielectric materials look extremely promising. However, wide spread deployment of these materials in modern integrated circuit fabrication processes presents some technological hurdles.
Specifically, in comparison with silicon dioxide, low-k carbon-doped oxide (CDO) materials typically have inferior mechanical properties due to the presence of ending methyl groups (—CH3), which are incorporated in the film in order to lower the k value of CDO materials. These mechanical properties include hardness, modulus, film residual stress, blanket film cracking threshold or limit, fracture toughness, etc. These properties are dependent primarily on the strength of the atomic bonds and their binding energies. CDO materials with inferior mechanical properties will tend to have adhesive failures (delamination) and cohesive failures (cracking) during the copper-low k integration and packaging steps. These failures are exacerbated by the increasing complexity of integrated circuits and frequently manifest with growing numbers of metallization layers. It is not uncommon for a modern IC design to require nine metallization layers, each with a separate dielectric layer. Each of these dielectric layers will have to withstand mechanical stresses from, for example, Chemical Mechanical Polishing (CMP) and/or thermal and mechanical stresses incurred during IC packaging operations.
There are a variety of methods used to improve the hardness and/or reduce the residual stress of CDO films. Examples include UV treatment and plasma treatments, etc. Some examples are presented in U.S. patent application Ser. No. 10/820,525, filed Apr. 7, 2004 by Wu, et al. and titled “Methods for Producing Low-k CDO Films with Low Residual Stress” and Van Cleemput et al., U.S. Pat. No. 6,340,628, which are both incorporated by reference herein. However, film hardness is not the only measure used to determine whether a film is acceptable for use in chip integration. It has been found that film toughness, cracking resistance, and resistance to crack propagation once a crack is formed are also important in order to ensure successful integration. Thus, there is a fundamental need for methods to improve the film toughness and cracking resistance of CDO films.